Method for manufacturing diode-connected transistor and image display device using the same

ABSTRACT

A method for manufacturing a diode-connected transistor includes forming a silicon layer on a substrate, a first insulation film on the silicon layer, and a gate electrode on the first insulation film. The method also includes forming a source region, a channel region, and a drain region in the silicon layer and forming a second insulation film on the gate electrode. A source electrode and a drain electrode are formed on the second insulation film and are coupled to the source region and the drain region, respectively. The method further includes coupling the drain electrode to the gate electrode through a contact hole that is vertically above the channel region.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. patent application Ser. No. 10/982,429, filed on Nov. 5, 2004 which claims priority to and the benefit of Korea Patent Application No. 2003-83586 filed on Nov. 24, 2003 in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.

BACKGROUND

(a) Field

The present invention relates to a display device. More specifically, the present invention relates to a method for improving an aperture ratio of an organic EL (electroluminescent) display device.

(b) Description of the Related Art

In general, an organic EL display electrically excites a phosphorous organic compound to emit light, and it voltage- or current-drives N×M organic emitting cells to display images. An organic emitting cell includes an anode, such as indium tin oxide (ITO), an organic thin film, and a cathode layer (metal). The organic thin film has a multi-layer structure including an emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) for maintaining balance between electrons and holes and improving emitting efficiencies. It further includes an electron injecting layer (EIL) and a hole injecting layer (HIL).

Methods for driving the organic emitting cells include a passive matrix method, and an active matrix method using thin film transistors (TFTs). In the passive matrix method, cathodes and anodes cross (i.e., cross over or intersect with) each other, and lines are selectively driven. On the other hand, in the active matrix method, a TFT is coupled to each ITO pixel electrode to thereby maintain the voltage by capacitance of a capacitor. The active matrix method is classified as a voltage programming method or a current programming method according to signal forms supplied for programming a voltage in the capacitor.

It is difficult for the conventional voltage-programming pixel circuit to obtain high gray scales due to the threshold voltage (V_(TH)) of a TFT and the deviation of the mobility of carriers caused by non-uniformity of the manufacturing process. For example, when a TFT is driven by a voltage of 3 volts (3V), the voltage is applied to a gate of the TFT at intervals of less than 12 mV (=3V/256) in order to represent 8-bit (256) gray scales. Therefore, for example, if the deviation of the threshold voltage of the TFT is 100 mV because of non-uniformity of a manufacturing process, it becomes difficult to represent the high gray scales.

In order to compensate for the deviation of the threshold voltage of the TFT, a diode-connected compensation transistor is conventionally coupled to the gate of a driving transistor.

The diode-connected transistor represents a transistor which substantially performs the same operation as that of the diode, and indicates a transistor having a gate and a drain which are coupled to each other as shown in FIGS. 1A and 1B.

FIG. 2 shows a plane view of a conventional diode-connected transistor, and FIG. 3 shows a cross-sectional view of FIG. 2 with respect to the reference of A-B.

As shown in FIGS. 2 and 3, a conventional diode-connected transistor includes a passivation layer 80, a drain electrode 32 contacting a drain region 21, a source electrode 22 contacting a source region 21, and a gate electrode 10. The drain electrode 32 is extended to reach the gate electrode 10, and the gate electrode 10 and the drain electrode 32 are coupled through a contact hole 72 in a second insulation film 70. This method reduces the aperture ratio of the organic EL display device since the area occupied by the diode-connected transistor is enlarged.

SUMMARY

In one embodiment of the present invention, a method for manufacturing a diode-connected transistor includes: forming a silicon layer on a substrate; forming a first insulation film on the silicon layer; forming a gate electrode on the first insulation film; forming a source region, a channel region, and a drain region in the silicon layer; forming a second insulation film on the gate electrode; forming a source electrode and a drain electrode on the second insulation film to project through the first and second insulation films so that the source electrode and the drain electrode are coupled to the source region and the drain region respectively; and coupling the drain electrode to the gate electrode through a contact hole in the insulation film, wherein the contact hole is formed above the channel region.

In another embodiment of the present invention, a method for manufacturing a diode-connected transistor includes: forming a silicon layer on a substrate; forming a first insulation film on the silicon layer; forming a gate electrode on the first insulation film; forming a source region, a channel region, and a drain region in the silicon layer; forming a second insulation film on the gate electrode; forming a source electrode and a drain electrode on the second insulation film to project through the first and second insulation films so that the source electrode and the drain electrode are coupled to the source region and the drain region, respectively. The drain electrode covers at least part of the channel region and the drain electrode and the gate electrode are coupled through a contact hole.

In yet another embodiment of the present invention, an image display device includes a plurality of data lines for transmitting data currents for display of image signals, a plurality of scan lines for transmitting select signals, and a plurality of pixel circuits formed at a plurality of pixels defined by the data lines and the scan lines, wherein the pixel circuit includes: a first transistor having a first electrode and a second electrode, having a capacitor between the first and second electrodes, the first transistor outputting a current which corresponds to a voltage, applied between the first and second electrodes, to a third electrode. A display element is coupled to the third electrode of the first transistor for displaying an image in correspondence to an amount of the applied current. A second transistor is also provided and has a first electrode coupled to the first electrode of the first transistor, a second electrode, and a third electrode. The second transistor is diode-connected. The image display system also includes a switch for transmitting a voltage applied to the data line to the second transistor in response to a select signal applied to the scan line. In this embodiment, the third electrode of the second transistor is coupled to the first electrode of the second transistor through a contact hole, and the contact hole is above a channel in a silicon layer.

In still yet another embodiment of the present invention, in a method for manufacturing an image display device including a pixel region for forming a pixel circuit and a driving region for driving the pixel circuit wherein the pixel circuit includes a diode-connected transistor, a method for manufacturing the diode-connected transistor includes: forming a semiconductor layer on a substrate, the semiconductor layer having a source region, a channel region and a drain region; forming a gate electrode with a gate insulation film, the gate electrode and the gate insulation film at least partially covering the channel region; forming an inter-layer insulation film on the gate electrode; forming a source electrode and a drain electrode on the inter-layer insulation film and coupling the source electrode and the drain electrode to the source region and the drain region, respectively. This embodiment also includes positioning the drain electrode to cover part of the inter-layer insulation film above at least part of the channel region, and coupling the drain electrode to the gate electrode through a contact hole in the inter-layer insulation film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a conventional diode-connected PMOS transistor.

FIG. 1B shows a conventional diode-connected NMOS transistor.

FIG. 2 shows a plane view of the diode-connected transistors of FIGS. 1A and 1B.

FIG. 3 shows a cross-sectional view along the line A-B of the diode connected transistor of FIG. 2.

FIG. 4 shows a pixel circuit of an organic EL display device.

FIG. 5 shows a plane view of a compensation transistor according to an exemplary embodiment of the present invention.

FIG. 6 shows a cross-sectional view of the compensation transistor according to an exemplary embodiment of the present invention.

FIG. 7 shows a plane view of a compensation transistor according to another exemplary embodiment of the present invention.

FIG. 8 shows another pixel circuit of an organic EL display device.

DETAILED DESCRIPTION

As shown in FIG. 4, a pixel circuit of an organic EL display device includes a driving transistor M1, a compensation transistor M2, switching transistors M3 and M4, a capacitor Cst, and an organic EL element OLED.

The driving transistor M1 controls the current flowing to the organic EL element OLED, and has a source coupled to a power VDD and a drain coupled to the organic EL element.

The compensation transistor M2 compensates for the deviation of the threshold voltage of the driving transistor M1, and has a gate coupled to the gate of the driving transistor M1. In this embodiment, the compensation transistor M2 is diode-connected.

The switching transistor M3 transmits a voltage from the data line Dm to the compensation transistor M2 in response to a select signal provided by the scan line Sn, and the switching transistor M4 transmits a precharge voltage Vp to the compensation transistor M2 in response to a select signal provided by a previous scan line Sn−1.

The capacitor Cst is coupled between the gate and the source of the driving transistor M1, and maintains the gate-source voltage of the driving transistor M1 at a constant voltage.

Referring to FIGS. 5 and 6, a method for manufacturing the compensation transistor M2 according to an exemplary embodiment of the present invention will be described.

FIG. 5 shows a plane view of the compensation transistor M2 according to an exemplary embodiment of the present invention, and FIG. 6 shows a cross-sectional view of the compensation transistor M2 according to an exemplary embodiment of the present invention.

As shown in FIGS. 5 and 6, a gate electrode 100 of the compensation transistor M2 and a drain electrode 320 are coupled by forming a contact hole 720, aligned with the gate electrode 100, in a second insulation film 700. A passivation layer 800 is formed above the second insulation film 700.

In detail, as shown in FIG. 6, a polycrystalline silicon layer 500 is formed on a transparent insulation substrate 400, and a first insulation film 600 made of SiO2 or SiNx is formed on the polycrystalline silicon layer 500.

The gate electrode 100 made of Al or Cr is formed on the first insulation film 600 so that the gate electrode 100 may cross the polycrystalline silicon layer 500.

The polycrystalline silicon layer 500 is doped with p-type dopant, excluding a region below the gate electrode 100. Regions doped with the dopant respectively form a source region 210 and a drain region 310, and an undoped region forms a channel region 510.

A source electrode 220 is formed on the source region 210, and the drain electrode 320 is formed on the drain region 310.

The drain electrode 320 contacts the gate electrode 100 so that the drain electrode 320 may cover part of the channel region 510 of the transistor M2, and the drain electrode 320 is coupled to the gate electrode 100 through a contact hole 720. In this embodiment, the contact hole 720 is above the channel 510 (i.e., covering, overlapping, or aligned in a vertical direction with the channel, with or without intervening elements therebetween).

Accordingly, the area occupied by the diode-connected transistor M2 is reduced, and the aperture ratio of the organic EL display device is improved.

Widths of the source and drain regions 210 and 310 are illustrated to be formed wider than those of the source and drain electrodes 220 and 320 in FIG. 5. Alternatively, as shown in FIG. 7, widths of the source and drain electrodes 220′ and 320′ can be formed much wider than areas of the source and drain regions 210 and 310.

The compensation transistor M2 of FIG. 5 is shown with a P channel transistor. Alternatively, the driving transistor M1 and the compensation transistor M2 can be N channel transistors. In this alternative embodiment (not shown), the drain electrode is formed to cover part of the channel area, and a contact hole for coupling the drain electrode and the gate electrode is formed above the channel of the transistor.

A diode-connected transistor has been shown as the compensation transistor in the voltage programming pixel circuit embodiments described above. However, a diode-connected transistor M3′ can also be used for the current programming pixel circuit as shown in FIG. 8. FIG. 8 shows first, second, third and fourth transistors M1′, M2, M3′ and M4, an organic element OLED and a capacitor Cst. Since the current programming pixel circuit is well known to a person skilled in the art, no corresponding description will be provided.

Further, the manufacturing method is applicable to circuits which use diode-connected transistors as well as the organic EL display device.

Although exemplary embodiments of the present invention have been described in detail hereinabove, it should be clearly understood that many variations and/or modifications of the basic inventive concept taught herein, which may appear to those skilled in the art, will still fall within the spirit and scope of the present invention, as defined in the appended claims, and equivalents thereof. 

1. A transistor, comprising: a semiconductor layer formed on a substrate, having a source region, a channel region and a drain region; a first insulation film formed on the semiconductor layer; a gate electrode formed on the first insulation film on the channel region of the semiconductor layer; a second insulation film formed on the gate electrode; a source electrode and a drain electrode formed on the second insulation film to project through the first and second insulation films so that the source electrode and the drain electrode are coupled to the source region and the drain region respectively, and the drain electrode covers at least part of the channel region; and a contact hole coupling the drain electrode and the gate electrode, formed in the second insulation film above the channel region.
 2. The transistor of claim 1, the semiconductor layer is a polycrystalline silicon layer.
 3. The transistor of claim 1, widths of the source region, the drain region, or both are wider than respective widths of the source electrode, the drain electrode, or both.
 4. The transistor of claim 1, widths of the source region, the drain region, or both are narrower than respective widths of the source electrode, the drain electrode, or both.
 5. A transistor, comprising: a semiconductor layer formed on a substrate, having a source region, a channel region and a drain region; a first insulation film formed on the semiconductor layer; a gate electrode formed on the first insulation film on the channel region of the semiconductor layer; a second insulation film formed on the gate electrode; a source electrode and a drain electrode formed on the second insulation film to project through the first and second insulation films so that the source electrode and the drain electrode are coupled to the source region and the drain region respectively, and one of the drain electrode and the source electrode covers at least part of the channel region; and a contact hole coupling the one of the drain electrode and the source electrode covered at least of the channel region and the gate electrode through.
 6. The transistor of claim 5, the semiconductor layer is a polycrystalline silicon layer.
 7. The transistor of claim 5, widths of the source region, the drain region, or both are wider than respective widths of the source electrode, the drain electrode, or both.
 8. The transistor of claim 5, widths of the source region, the drain region, or both are narrower than respective widths of the source electrode, the drain electrode, or both. 